The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology which is effective if applied to a semiconductor integrated circuit device composed of memory cells having a full CMIS (Complementary Metal Insulator Semiconductor) structure.
The memory cells of an SRAM (i.e., Static Random Access Memory) each storing information of 1 [bit] are arranged at intersections between word lines and complementary data lines (complementary data line pairs). A plurality of these SRAM memory cells are arranged in a matrix in the extending directions of the word lines and the complementary data lines to constitute a memory cell array.
Each memory cell of an SRAM is composed of a flip-flop circuit (or an operational amplifier) and two transfer MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The flip-flop circuit is constituted as an information storage unit comprising two drive MOSFETs and two load elements. The two transfer MOSFETs and the two drive MOSFETs are of n-channel conduction type.
The memory cell of the SRAM is exemplified by the full CMOS structure in which the load elements are made up of p-channel conduction type load MOSFETs. The memory cell of this full CMOS structure has its p-channel type load MOSFET, n-channel type drive MOSFET and n-channel type transfer MOSFET all formed in a semiconductor substrate. The memory cell of this full CMOS structure is featured by: (1) a low power consumption; (2) a high speed operation; (3) necessity for neither high resistance polysilicon nor polysilicon PMOS to be laminated over the MOSFETs, but for only the CMOS thereby to simplify the manufacturing process; (4) a stable operation even at a low voltage by the drive of the load MOSFETs; and (5) a high resistance to alpha rays. Thus, the memory cell of the full CMOS structure can be widely used in a super-high speed memory such as a large-sized computer, thanks to the aforementioned feature (2), and in a storage unit of a CMOS logic LSI or microprocessor LSI, thanks to the aforementioned feature (3).
In the memory cell having the full CMOS structure, the source region of the n-channel type drive MOSFET is connected to an operation power line fixed at the operation potential (e.g., -2.5 [V]), and the source region of the p-channel type load MISFET is connected to a reference power line fixed at a reference potential (e.g., 0 [V]). Moreover, the drain regions of the n-channel type drive MOSFET and the p-channel type load MOSFET are connected to each other through intra-cell wirings. The power supply line, the reference potential line and the internal wirings are formed of the first level metal wiring layer. Still moreover, either the source region or the drain region of the n-channel type transfer MOSFET is connected through the intra-cell wirings with complementary data lines formed of the second level metal wiring layer.
Incidentally, the memory cell of the SRAM having the aforementioned complete CMOS structure is disclosed in Japanese Patent Application No. 294576/1992, for example.